1. Field of the Invention
The present invention relates to an analog-to-digital converter converting an analog signal to a digital signal.
2. Description of the Related Art
Recently, analog-to-digital converters (ADCs) converting analog signals to digital signals have been used in various fields. FIG. 16 illustrates a VF type ADC converting voltage to frequency disclosed in Japanese Patent Laid-Open No. 2007-139700.
In FIG. 16, a voltage-to-pulse converter 100 includes an input switching circuit 104; an integrator output guiding unit 105 as a voltage guiding unit; an integrator 108; first and second comparators 112 and 113 (window comparator); an RS latch circuit 114; first and second integrator output error detection circuits 116 and 119; OR circuits 120 and 122; first and second comparator continuous output judgement circuits 117 and 118; and a flip-flop (FF) 123 as a flag output part.
Here, the input switching circuit 104 switches a connection between a CS+ terminal and a CS− terminal, and a positive or negative input terminal of the integrator 108. In addition, the integrator 108 includes a differential amplifier 111; a resistor 109, one end of which is connected to the − terminal (inverting input terminal) of the differential amplifier 111; and a capacitor 110 connected between an output of the differential amplifier 111 and the − terminal.
The integrator output guiding unit 105 includes switches 106 and 107, one end of which is connected to nodes 106a and 106b respectively and the other end of which is connected to a reference potential. The integrator output guiding unit 105 guides an output of the integrator 108 to the vicinity of a first or second detection voltage.
The first and second comparators 112 and 113 detect the voltage from the output of the integrator 108 to a first detection voltage (1V) and a second detection voltage (2V) higher than the first detection voltage.
The FF 123 outputs a flag FLAG based on the comparison result of the first and second comparators 112 and 113. An inverter 124 outputs an output signal CKOUT having a frequency corresponding to an input voltage.
By such an operation, the circuit illustrated in FIG. 16 converts the input voltage generated between the CS+terminal 101 and the CS-terminal 102 to a pulse. The input switching circuit 104 switches the above connection based on the flag FLAG and the output signal CKOUT.
In addition, FIG. 17 illustrates an ADC disclosed in Japanese Patent Laid-Open No. 62-289016. The ADC illustrated in FIG. 17 supplies an input analog voltage via an adder 201 to an ADC 202 which converts it to an output digital value. The ADC illustrated in FIG. 17 feeds back an offset correction voltage from a feedback circuit 203 to the adder 201. If the analog voltage does not contain a residual noise exceeding a predetermined level, dither is supplied from a dither generation circuit 204 to the adder 201 so as to superimpose noise on the input analog voltage. The feedback circuit 203 supplies a correction voltage based on the output digital values to the adder 201 so that the probabilities of occurrence of the upper and lower codes are equal except a specific output code of the output digital values. This corrects an offset error between a specific level of the input analog voltage and a specific code of the output digital value corresponding to the specific level.
However, if there is an offset in the integrator 108 of the analog-to-digital converter disclosed in the Japanese Patent Laid-Open No. 2007-139700, the offset is superimposed on the input signal and integrated by the integrator. For this reason, there is a problem in that a dead band region occurs in the analog-to-digital converter, thereby reducing the accuracy of the analog-to-digital converter. In particular, the smaller the absolute value of an input signal, the greater the influence of the offset.
Moreover, the analog-to-digital converter disclosed in Japanese Patent Laid-Open No. 62-289016 uses dither to automatically correct an offset error of the AD conversion result. However, it is difficult for the analog-to-digital converter disclosed in Japanese Patent Laid-Open No. 62-289016 to improve the AD conversion accuracy when the input signal has a small absolute value.